Wednesday, March 02, 2005
My Questions
Hi folks,
here are the questions I have compiled while reading books/articles etc...
I hope these questions help you in understanding/reasoning the subject ......
1.Why does a CMOS inverter has finite gain in transition region ?
or ( to put it the other way)
What is the reason for not having a ideal VTC for a CMOS inverter?
2.In what way is Memory design different from Random logic design?
or ( to put it the other way)
How is Memory design different from combo logic design?
3.Why don't we use a FlipFlop (say a D flop) as a memory cell?
4.Why is it essential to have data stable in the metastable window period of a FlipFLop/Latch? What is the actual cause forcing such requirement ( setup/hold time requirements)?
5.Why Sub-threshold leakage current increases with decrease in Vt?
6.Is Technology scaling all advantageous? Explain.
7.What happens to the VTC of a CMOS inverter if Vdd is reduced ?
8.What is the optimum value of Vdd for a CMOS inverter?
9.Why BiCMOS in not being used extensively inspite of it's advantages over CMOS?
10.A CMOS inverter has it's o/p fed back to it's input. What will be the function of the ckt?
11.There is a chain of inverters with the o/p fedback to i/p. What will be the frequency of oscillation if Tp of the inverter is 2ns and the no: of inverters is
a) 3 b) 25 c) 10
12)For routing power in a process techhnology that supports 3 level metal layers, which metal layer will you choose and why ?
13) In an inverter transition region of VTC is not used.If VTC of a inverter has gain of 700 in forbidden region and another inverter has a gain of 10,000 which inverter would you prefer? What if inverter has a gain of 0.8 in transition region?
14)Differentiate Noise Margin and Noise Immunity of a CMOS inverter.
15)In CMOS i/p current is zero. Why don't we still have a large fanout , what keeps from having a large fanout?
16) What should be the slope of i/ps to a gate ( i/p rise and fall times ) large/small from delay and power consumpton point of view ?
17) How many stages atleast are needed for a ring oscillator to be operational ? why?
18)What is the purpose of Epitaxial layer?
19)What is channel stop implant used for ?
20) Delay is critical parameter in a memory. How will you reduce this delay at the time of circuit
design. what are the various methods followed?
21) What is FAMOS and FLOTOX? Where are they used?
22) What are the different tunneling mechnaisms you know? Expalin.
23) What is the advantage of FLASH memory over EEPROM?
24) What
here are the questions I have compiled while reading books/articles etc...
I hope these questions help you in understanding/reasoning the subject ......
1.Why does a CMOS inverter has finite gain in transition region ?
or ( to put it the other way)
What is the reason for not having a ideal VTC for a CMOS inverter?
2.In what way is Memory design different from Random logic design?
or ( to put it the other way)
How is Memory design different from combo logic design?
3.Why don't we use a FlipFlop (say a D flop) as a memory cell?
4.Why is it essential to have data stable in the metastable window period of a FlipFLop/Latch? What is the actual cause forcing such requirement ( setup/hold time requirements)?
5.Why Sub-threshold leakage current increases with decrease in Vt?
6.Is Technology scaling all advantageous? Explain.
7.What happens to the VTC of a CMOS inverter if Vdd is reduced ?
8.What is the optimum value of Vdd for a CMOS inverter?
9.Why BiCMOS in not being used extensively inspite of it's advantages over CMOS?
10.A CMOS inverter has it's o/p fed back to it's input. What will be the function of the ckt?
11.There is a chain of inverters with the o/p fedback to i/p. What will be the frequency of oscillation if Tp of the inverter is 2ns and the no: of inverters is
a) 3 b) 25 c) 10
12)For routing power in a process techhnology that supports 3 level metal layers, which metal layer will you choose and why ?
13) In an inverter transition region of VTC is not used.If VTC of a inverter has gain of 700 in forbidden region and another inverter has a gain of 10,000 which inverter would you prefer? What if inverter has a gain of 0.8 in transition region?
14)Differentiate Noise Margin and Noise Immunity of a CMOS inverter.
15)In CMOS i/p current is zero. Why don't we still have a large fanout , what keeps from having a large fanout?
16) What should be the slope of i/ps to a gate ( i/p rise and fall times ) large/small from delay and power consumpton point of view ?
17) How many stages atleast are needed for a ring oscillator to be operational ? why?
18)What is the purpose of Epitaxial layer?
19)What is channel stop implant used for ?
20) Delay is critical parameter in a memory. How will you reduce this delay at the time of circuit
design. what are the various methods followed?
21) What is FAMOS and FLOTOX? Where are they used?
22) What are the different tunneling mechnaisms you know? Expalin.
23) What is the advantage of FLASH memory over EEPROM?
24) What
