Tuesday, February 22, 2005
Computer Organization Questions
COMPUTER ORGANIZATION:
Hi folks,
I thought, Computer organization is required for a VLSI design engineer.Intel,amd,....do processor design and expect you to have "what is what" knowledge, you may not be doing the architecture development but nothing wrong in knowing "what is what "......
these are the Questions I have collected from my frens (and personal experience).
1.What is a Cache? What is it used for? What is the principle behind it?
2.what should be the size of a cache -- large/small?
3. What is a cache hit and cache hit ratio?
4. what are the various mappings used in Cache?
( direct, assosciative , set-assosciative )
5.What are the stages of a 5 stage DLX pipeline?
6. What are bubbles in a pipeline ?
7. What are HAZARDS in a pipelined system?
8. What is the ideal throughput of a N stage pipeline system? What prevents from achieving the
ideal throughput ? Is it better to have a 5 stage pipeline or 20 stage pipeline?
9.Expand TLB. what is it used for?
10. Name some Bus standards u know. Compare them.
11.Explain purpose of cache in a single Processor system and a double processor system with a
separate cache for each processor.
12.Explain difference between "Write through" and "Write back" caches.
13.What is MESI ?
14.What is Snooping?
15.Swap two 8-bit registers without using any other register.
16.Differentiate Overflow and Carry flag.
17.Differntiate Superscalar and VLIW processors.
18.What is MicroProgram control and Hardwired control?
19.What is Von-Numan architecture and Harvard architecture ?
Which one is used for MicroProcessor and which one forDigital signal Processor? Why?
20.What is Branch Prediction and BTB?
21.What is virtual memory?
22.What is cache Cohorency?
23.Differntiate MicroProcessor and MicroController.
24.Processor is busy , but you want to perform some task . How will you do that?
25.What is ACBF ( hex number) divided by 16 , give Quotient and remainder?
26.Given cache size is 64KB , Block size is 32B and the cache is two-way set assosciative.
For a 32-bit physical address, give the division between block offset, index and tag.
27.Differentiate RISC and CISC. Is RISC always fast?
28. How is a DSP different from a GPP?
Give me feedback
Hi folks,
I thought, Computer organization is required for a VLSI design engineer.Intel,amd,....do processor design and expect you to have "what is what" knowledge, you may not be doing the architecture development but nothing wrong in knowing "what is what "......
these are the Questions I have collected from my frens (and personal experience).
1.What is a Cache? What is it used for? What is the principle behind it?
2.what should be the size of a cache -- large/small?
3. What is a cache hit and cache hit ratio?
4. what are the various mappings used in Cache?
( direct, assosciative , set-assosciative )
5.What are the stages of a 5 stage DLX pipeline?
6. What are bubbles in a pipeline ?
7. What are HAZARDS in a pipelined system?
8. What is the ideal throughput of a N stage pipeline system? What prevents from achieving the
ideal throughput ? Is it better to have a 5 stage pipeline or 20 stage pipeline?
9.Expand TLB. what is it used for?
10. Name some Bus standards u know. Compare them.
11.Explain purpose of cache in a single Processor system and a double processor system with a
separate cache for each processor.
12.Explain difference between "Write through" and "Write back" caches.
13.What is MESI ?
14.What is Snooping?
15.Swap two 8-bit registers without using any other register.
16.Differentiate Overflow and Carry flag.
17.Differntiate Superscalar and VLIW processors.
18.What is MicroProgram control and Hardwired control?
19.What is Von-Numan architecture and Harvard architecture ?
Which one is used for MicroProcessor and which one forDigital signal Processor? Why?
20.What is Branch Prediction and BTB?
21.What is virtual memory?
22.What is cache Cohorency?
23.Differntiate MicroProcessor and MicroController.
24.Processor is busy , but you want to perform some task . How will you do that?
25.What is ACBF ( hex number) divided by 16 , give Quotient and remainder?
26.Given cache size is 64KB , Block size is 32B and the cache is two-way set assosciative.
For a 32-bit physical address, give the division between block offset, index and tag.
27.Differentiate RISC and CISC. Is RISC always fast?
28. How is a DSP different from a GPP?
Give me feedback
# posted by blograma @ 2:26 AM 
