Interview Questions - VLSI/ASIC/IC design

Hi folks,
here are the questions I have compiled while reading books/articles etc...
I hope these questions help you in understanding/reasoning the subject ......

1.Why does a CMOS inverter has finite gain in transition region ?
or ( to put it the other way)
What is the reason for not having a ideal VTC for a CMOS inverter?

2.In what way is Memory design different from Random logic design?
or ( to put it the other way)
How is Memory design different from combo logic design?

3.Why don't we use a FlipFlop (say a D flop) as a memory cell?

4.Why is it essential to have data stable in the metastable window period of a FlipFLop/Latch? What is the actual cause forcing such requirement ( setup/hold time requirements)?

5.Why Sub-threshold leakage current increases with decrease in Vt?

6.Is Technology scaling all advantageous? Explain.

7.What happens to the VTC of a CMOS inverter if Vdd is reduced ?

8.What is the optimum value of Vdd for a CMOS inverter?

9.Why BiCMOS in not being used extensively inspite of it's advantages over CMOS?

10.A CMOS inverter has it's o/p fed back to it's input. What will be the function of the ckt?

11.There is a chain of inverters with the o/p fedback to i/p. What will be the frequency of oscillation if Tp of the inverter is 2ns and the no: of inverters is
a) 3 b) 25 c) 10

12)For routing power in a process techhnology that supports 3 level metal layers, which metal layer will you choose and why ?

13) In an inverter transition region of VTC is not used.If VTC of a inverter has gain of 700 in forbidden region and another inverter has a gain of 10,000 which inverter would you prefer? What if inverter has a gain of 0.8 in transition region?

14)Differentiate Noise Margin and Noise Immunity of a CMOS inverter.

15)In CMOS i/p current is zero. Why don't we still have a large fanout , what keeps from having a large fanout?

16) What should be the slope of i/ps to a gate ( i/p rise and fall times ) large/small from delay and power consumpton point of view ?

17) How many stages atleast are needed for a ring oscillator to be operational ? why?

18)What is the purpose of Epitaxial layer?

19)What is channel stop implant used for ?

20) Delay is critical parameter in a memory. How will you reduce this delay at the time of circuit
design. what are the various methods followed?

21) What is FAMOS and FLOTOX? Where are they used?

22) What are the different tunneling mechnaisms you know? Expalin.

23) What is the advantage of FLASH memory over EEPROM?

24) What

Hi folks,
I have collected these QUestions from frens, web, campus experience .....
If u have Questions please send me @ my mail id. I'll update the blog.

1. A BJT has it's base connected to i/p ( sinusoidal signal with Vp = 5v , Vpp = 10v), collector
tied to Vcc = 5v and emitter connected to Vee= -5v through 100K resistor.
Plot output. [MOTOROLA]

2. A PLL has it's direct i/p from a divide by N counter and feedback i/p from divide by M
counter. what would be the output frequency? [SASKEN]

3.For low noise applications Transistors used should be wide or narrow ? why ? [Analog]

4.What is Miller Compensation? [TI]

5.For an Op-Amp, offset at the input is 5mv.If Voltage Gain is 10,000 and Vsat = +/-15v,
what is the o/p voltage with both i/ps of Op-Amp are shorted. [intel]

6.An Op-Amp has it's o/p connected back to it's non-inverting terminal and input is given to
the same i/p terminal with the other i/p terminal grounded. what will be the o/p or th circuit acts as a____________ ? [TI]

7.A BJT has it's base connected to a 1V dc battery through 52K resistor, it's emitter is grounded
and collector is connected to Vcc=10v through 10K(Rc) resistor.Calculate the currnet flowing through resistor,Rc(10K ) ,if Beta = 200. [MOTOROLA]

8.Given a RL ckt ( with o/p taken across L ) and a square wave applied as i/p to the series RL ckt with peak value of +/- Vmax. Plot the o/p for different normalized time constants ( small, medium, large). [ST]

9.Given an Op-Amp ckt with i/p applied to non-inverting i/p terminal and o/p fedback to oinverting terminal with resistive feedback and beta( feedback factor equal to 1/2).
Input applied is sinusoidal signal with peak value of 4 V. Op-Amp supply voltages are +/-5V.
Plot output. [ST].

10.If X1(t) is a ectangular pulse from -T to T with amplitude of 1 and X2(t) is a series of three delta functions at -3T O and 3T.Plot X1(t) * X2(t) where * is symbol for convolution.[ST].

11.What is the circut given below

this resistor shunts inverter-----/\/\/\-------
input _______/\/\/\/----0-------INV------0--------o/p



INV is a inverter.

a) Latch b) Amplifier c) Schmitt trigger [Analog]

12.In a BJT ckt i/p to the base of the BJT is given through a resistor to which a capacitor is connected in parallel.What is the capacitor used for
a) to improve switching b) dc coupling c) ac coupling [Analog]

COMPUTER ORGANIZATION:
Hi folks,
I thought, Computer organization is required for a VLSI design engineer.Intel,amd,....do processor design and expect you to have "what is what" knowledge, you may not be doing the architecture development but nothing wrong in knowing "what is what "......
these are the Questions I have collected from my frens (and personal experience).


1.What is a Cache? What is it used for? What is the principle behind it?

2.what should be the size of a cache -- large/small?

3. What is a cache hit and cache hit ratio?

4. what are the various mappings used in Cache?
( direct, assosciative , set-assosciative )

5.What are the stages of a 5 stage DLX pipeline?

6. What are bubbles in a pipeline ?

7. What are HAZARDS in a pipelined system?

8. What is the ideal throughput of a N stage pipeline system? What prevents from achieving the
ideal throughput ? Is it better to have a 5 stage pipeline or 20 stage pipeline?

9.Expand TLB. what is it used for?

10. Name some Bus standards u know. Compare them.

11.Explain purpose of cache in a single Processor system and a double processor system with a
separate cache for each processor.

12.Explain difference between "Write through" and "Write back" caches.

13.What is MESI ?

14.What is Snooping?

15.Swap two 8-bit registers without using any other register.

16.Differentiate Overflow and Carry flag.

17.Differntiate Superscalar and VLIW processors.

18.What is MicroProgram control and Hardwired control?

19.What is Von-Numan architecture and Harvard architecture ?
Which one is used for MicroProcessor and which one forDigital signal Processor? Why?

20.What is Branch Prediction and BTB?

21.What is virtual memory?

22.What is cache Cohorency?

23.Differntiate MicroProcessor and MicroController.

24.Processor is busy , but you want to perform some task . How will you do that?

25.What is ACBF ( hex number) divided by 16 , give Quotient and remainder?

26.Given cache size is 64KB , Block size is 32B and the cache is two-way set assosciative.
For a 32-bit physical address, give the division between block offset, index and tag.

27.Differentiate RISC and CISC. Is RISC always fast?

28. How is a DSP different from a GPP?


Give me feedback

Hi folks,
the Questions I am posting here are what I have collected from my friends, web, my campus tests. I thank my frens for their help.

These Questions are asked by Companies like Motorola,TI,Intel,Nvidia,Atrenta,ST,Agilent,
Sasken,AMD,.......

DIGITAL DESIGN

1.Using a 2:1 Mux realize the following
a) NOT gate b) AND gate c) OR gate d) Ex-OR gate e) Ex-NOR gate
f) NAND gate g) NOR gate h) Latch i) FlipFlop
hint : Use Shannon's Expansion , get expression in the form of Mux equation
muxout = sel_bar * Input0 + sel*Input1.

2.Using Combo logic Multiply Clock by two ( freq of clock at o/p = 2* freq at i/p)

3.Realize transistor level circuit for
Y = { [ (ABC+Abar)bar ] * (AB + Bbar) }

4.Given/using a Positive Trigger as input generate Square wave.

5. Question on Static Hazards
AND gate 1 has two i/ps A , sel
AND gate 2 has two i/ps B,sel_bar
output of these AND gates are given as i/p to ex-or gate
Tand = Tex-or= 2ns, Tinv ( used for sel_bar ) = 1ns

find Glitch width and draw the hazard-free circuit
hint: See switching theory book by Kohavi

6.Draw FSM for "0101" sequence detector and code it in Verilog/VHDL.
How many FFs are needed?

7.Given a 8 bit number how would you check whether it is a palindrome or not???

8.Two FFs are cascaded with combo logic in between ( Q of FF1 to D of FF2)
Tcombo,min = 1ns and Tcombo,max = 3ns
Tsetup = Thold = 2ns, Tclk = 10ns, Tclock-to-Q = 2ns
check for Setup and hold time violations.

9.What is Synchronizer used for ? draw the ciruit and comment on sizing of Txs.
hint : see DIGITAL INTEGRATED CIRCUITS book by Rabaey.

10.Draw Tx level ckt for Y= AB + AC + BD + CD.

11.What is RACE condition ? How to avoid it?

12.Using D FF and combo logic realize T FF.

13.Using D FF and COMBO logic realize JK FF.

14.What are the advantages and disadvanteages of Dynamic Logic ?

15.Draw NAND and NOR equivalents of CMOS inverter for equal rise and fall times.
hint : see DIGITAL INTEGRATED CIRCUITS by Rabaey.

16. Is it possible to have negative setup and hold times ? Explain.

17.A 7 bit ring counter has initial state 0100010 after how many clock cycles it will return to
initial state?

18. Which device is fast BJT or MOS? Why ?

19. A 4 bit shift register has _______ number of states.

20. What is Mealy FSM and Moore FSM? Which one is fast?

21.Give adv and disadv of Mealy and Moore FSMs? Give examples of applications of both.

22.Swap two 8-bit registers without using another register.
hint : use boolean logic

23.Realize a two i/p AND gate using Ex-OR gate .
hint: don't waste time , come 2 a conclusion , ...... ya u r right.... :-)

24.Describe an FSM to detect three successive coin tosses that result in Heads.

25.In what cases do you need to double clock a signal before presneting it to a Synchronous state
machine?

26.You have a driver that drives a long signal and connects to an i/p device. At the i/p there is
either overshoot or undershoot or signal threshold violations. What can be done to correct
this problem?

27.What is a Silicon Compiler and a Memory Compiler used for?

28.To realize a 4x4 multiplier using ROM, what is the size of ROM needed?

29.In a system there are two modules A and B. A is operating at 25 MHz and B at 25 KHz
From module A if a pulse of width equal to width of clock ( 1/25 Micro seconds) is sent, How
ensure that the pulse will be correctly received at module B without using handshaking or
Buffers like FIFO?

30.A D FF has its D i/p from a MUX. MUX input0 is connected to external i/p and MUXi
input1 is connected to output of D FF ( Q ) through combo block(i.e: feedback of o/p to i/p
thru combo block). If Mux delay is 0 ns and
Tsetup = 3ns, Thold = 2ns , TClock-to-Q = 1ns
What is the max frequency of the circuit with and without feedbak?

31.Why PMOS Tx is made 2.5 times wider than NMOS ?

32.If PMOS and NMOS Txs are interchanged in a CMOS inverter, what does it work like?

33.Draw Ids-Vds curve of a MOSFET with
a)increasing VGS, b) increasing W, c) considering Channel Length modulation

34.Why MOSFET goes into saturation and what type of current flows ( drift/diffusion) at
saturation?
(or)
If channel is pinched of how current flows from source to drain ?

35.List variuos Capacitances in a MOS device and their approximate values in Linear ,
saturaiton and cut-off regions.

36.Explain VTC of a CMOS inverter .what is the effect of channel length modulation in VTC ?

37.How to increase gain of a CMOS inverter in transition region ?On what factors does it
depend?

38. What is Noise Margin, Noise Immunity? differentiate.

39.What is regenerative property of a CMOS inverter? explain with graphs.

40.What is Switching/logic threshold of a CMOS inverter ? How to change it?

41.How to measure Noise Margin?

42.What is Body effect?

43.What is CMOS latchup ? how to avoid it?

44.What is Electromigration ? How to avoid it ?

45.What is ESD ? How to avoid it?

46.What is Ground Bounce ? How to avoid it?

47.Why don't you use a NMOS/PMOS as a TG?

48.What is Full scaling and constant voltage scaling ?

49.Why scaling is done?

50. If a technology is scaled by 30 % ( VDD also ), how the following change
a) Cox,Cg b) Power c) Area d) Delay.

51.GIve the Expression for Elmore delay and penfield Rubenstein delay models.

52.Why NAND logic is preferred in CMOS ?

53.What happpens if we increase number of contacts and vias from one metal layer to another?

54.Draw a 2 i/p NAND gate and explain sizing regarding Vth and rise/fall times.

55.What are limitations in increasing Vdd to reduce intrinsic dcelay?

56.What happens to delay if we include a resistence at the o/p of a cmos ckt?

57.What is crosstalk ? On what factors does it depend?

58.What are various kinds of power dissipation in CMOS circuits?

59.What are the disadvantages of scaling?

60.You have three adjacent parallel metal lines.Two out of phase signals pass through outer
lines.Draw the signal in central metal line due to interference. repeat for inphase signals
in the outer lines.

61.What happens if we increase no: of contacts or vias from one metal layer to another?

62.Draw Tx level ckt for a 2-i/p NAND gate and explain sizing considering
a) Logic threshold b) equal rise and fall times.

63. Why is it preferred to have logic threshold at Vdd/2 ?

64.What is Self-loading ?

65.Let A and B are inputs to a two i/p NAND gate, which signal should be close to the output
a) if signal A arrives later than signal B,
b) if signal B has higher switching activity than signal A,

66.Why fan-in of gates is resricted to 4 ?What is done to have large fan-in ?

67.Draw Stick diagram of a NOR gate and optimize it.

68.Give various methods used for reducing power in CMOS ciruits.

69.What is charge sharing ? Explain charge sharing while sampling data from a bus.

70.When driving a large capacitive load why do we use a chain of inverters with progressive
increase in size, instead of having a large buffer?

71.Explain difference between normal Buffers and Clock buffers.

72.Mention algorithms used for CLOCK distribution.

73.While laying out a large( wide) Transistor , why do we connect small transistors in parallel
rather than laying out a Tx with large width?

74.Why don't we use NMOS or PMOS as a switch?

75.Draw 6T SRAM cell . Explain read and write operation.
which one takes more time read/write ? why?

76.Draw a Differntial Sense amplifier and expalin its operation.

77.Draw a Cross coupled Snese amp and expalin its operation.

78.What is a double stage Differential sense Amplifier? what is it needed for?

79.Comment on sizing of Access Tx used in 6T SRAM cell.

80.Which one is fast NAND/ NOR ROM ?Give applications of each?

81.In memory design interconnect delay becomes critical , How is it reduced?

82.How does size of a PMOS pull up Tx affect performance of a 6T SRAM cell?

83.Explain sizing of variuos Txs used in SRAM cell.

84.What is critical path in SRAM?

85.In SRAM which metal layers would you prefer for word and bit lines?why?

86.How do you model SRAM in RTL ?

87.For an AND-OR implementation of a 2:1 Mux, how would you check for stuck-at-faults at
internal nodes?

88. Mention algorithms used for Stuck-at-fault analysis.

89.What is the differnce between testing and verification?

90.What Kind of circuit is this
A and B are inputs to an AND gate
AND gate output goes to one i/p of OR gate
The other i/p of OR gate comes from a Ex-OR gate
inputs to the Ex-OR gate are C and the output of the OR gate
( final output fedback to i/p )
combo/sequential?
synchronous/asynchronous?

91.Realize the boolean function
Y= A'B'C +A'BC+ABC+ABC'+AB'C
a) using 2-i/p and 3-i/p NAND gate,
b) using 2-i/p and 3-i/p NOR gate
c) using AOI gate
d) using inverter

92.What is the importance of SCAN in a digital system?

93. A Ex-OR B = C, Prove that
a) B Ex-OR C = A,
b) A Ex-OR B Ex-OR C = 0.

94.Construct a test pattern that can detect stuck-at-1 fault in the ckt given below
NAND gate NAND1 has two i/ps C and D
NAND gate NAND2 has two i/ps A and Y
AND gate has o/ps of NAND gates NAND1 and NAND2 as i/ps
and its o/p is Y ( this is fedback to i/p of NAND gate NAND2)

95.In an Op-Amp ckt i/p offest is 5mv, Voltage gain = 10,000, Vsat = +/- 15v.Find o/p voltage.

96.Draw P-n/w for the function Y = ( (AB+C) D)'.

97.Realize JK FF using D FF and MUX.

98.Realize the function Y= A + BC' + BC ( A + B) using 2:1 Mux.

99.For the circuit given below
D FF "DFF1" has its D i/p,D1, connected to o/p of Ex-OR "Ex-OR1"gate.
D FF "DFF2" has its D i/p,D2, connected to o/p of Ex-OR gate "Ex-OR1".
i/ps of Ex-OR gate "Ex-OR1" are o/ps of "DFF1" and "DFF2" ( Q1 and Q2)
CLK i/p of "DFF1" is connected directly to clock signal and CLK i/p of "DFF2"
is connected to inverted clock signal ( clcok signal goes to DFF2 thru inverter).
What is the realtion between input and output frequencies?

100.Design a Synchronous ckt for the following clock waveform
CLK ---> thrice the CLK period ---> half the period of i/p

101.What are setup and hold times of a FF? What happens if we don't consider them when
designing a digital circuit?

102.Two D FFs, "DFF1" and "DFF2" are cascaded, if Tsetup = Thold = 2ns and Twire = 0ns.What is the max Clock frequency for the ckt ? If DFF2 is negative edge triggered D FF
then what is the maximum clock frequency?

103.What is a FIFO buffer ? What is a FIFO buffer used for ?Give example.

104.How can you make sure that Glitches does not occur in a circuit at logic level?

105.What is the function of a D FF whose Complemented o/p ( Qbar ) is connected to it's
input,D. What is the max clock frequency that can be used for it?

106.What happens if Setup violation occurs ? what happens if Hold violation occurs? Can a circuit have both setup and hold violations? Is it possible to have Setup and hold violations together on the same path?

107. Which one will have less switching activity ?
a) Tree real;ization or b) chain realization .

108.Two D FFs,DFF1 and DFF2 are cscaded and clock arrives late at the clcok input of DFF2.
What happens if the delay ( in path from clock signal to clk i/p of DFF2) is large?How can this problem be solved?

109.Design a divide-by-3 sequential circuit with 50% duty cycle.

110.Draw the circuit of a TG based Latch.

111. _________

i/p ------------Buffer-----------o/p
In the above circuit, what is the purpose of the buffer.(Note that o/p is fedback to i/p)?
Is it redundant /necessary to have a buffer?

112.What is the o/p of the ciruit given below
2-i/p Ex-OR "Ex-OR1" has its i/ps tied to X,
2-i/p Ex-OR "Ex-OR2" has one of it's i/p connected to o/p of "Ex-OR1"
and the other i/p connected to X.
2-i/p Ex-OR "Ex-OR3" has one of it's i/p connected to o/p of "Ex-OR2"
and the other i/p connected to X.
What is the o/p of the circuit( o/p of "Ex-OR3").

113.Given a Circular disk with a sector of 45 degrees painted in blue. Two sensors are given and they can detect change in color. Design a circuit with minimum number of gates to detect the direction of the disk when it is rotated.

114.Given two transparent latches, realize a positive edge triggered D FF using minimum number of gates.

115.How many 2:1 Muxes are needed to realize a 16:1 Mux?

116.What is metastability? Why it occurs ? How to avoid it?

117.Convert a 2-i/p NAND gate to an inverter in two different ways.

118.Realize a T FF using 2:1 Muxes and few gates.

119.Realize D FF from RS latch ( not Flip Flop).

120.What is the difference between EEPROM and Flash Memory?

121.Define Clock skew. What are the causes for it ? How Positive skew effects the system?

122.Define Clock jitter and differentiate skew and jitter.How clock jitter effects the system?

123.Which one is good Synchronous reset or Asynchronous reset?

124.Describe an FSM to detect the string "abca" if i/ps are a,b,c,d. Code it in verilog/VHDL.

125.Change rise and fall times of a CMOS inverter without changing W/L ratios.
hint: rise and fall time depend on current drive available.

126.What are setup and hold times? what do they signify ? which one is critical for estimating maximum clock frequency?

127.Suppose you have a combo ckt b/w two registers driven by a clock.If the delay of Combo ckt is larger than the clock period, then how would you overcome the problem?

128.The answer to the above question is break the combo ckt ( functionality of combo into simple functions) and pipeline the combo block.What is the penalty in doing so?

129.Draw the ckts of TG based D latch and D FlipFlop(positive edge triggered).
how would you reduce load on the clock signal? what is the penalty in doing so?

130.Realize Ex-OR using TGs and modify to Ex-NOR gate (without complementing o/p).

131.Design an FSM to give modulo-3 counter when input X=0 and modulo-4 counter when input
X=1.

132.What is clock feedthrough?

133.Given a Clock signal, generate nonoverlapping clcoks ( clock and clock_bar) using Combo logic.

134. What happens to VTC of a CMOS inverter, if supply voltage is reduced?

135.What are the limitations on reducing Vdd from delay point of view and from noise point of view?

136.Design a logic circuit using AOI configuration sich that if input a=1, output Y = AB+CD
else Y=DE + CF.

137.What is charge sharing? how to avoid it?

138.Design a ckt that clips every alternate clock pulse.

139.If A ? B = C and A?C = B, then what is the operator "?".

140.Dynamic circuits with feedback are called _________________?

141.Design a circuit to count No: of ones in a 7-bit binary number ( data comes in parallel).
(do not do it bit by bit)

142.Generate a square wave using Mux.

143.Draw CMOS ckt for a Tri-state Buffer.Realize a 2:1 Mux using Tri-state Buffer.

I'll be back with more Questuions...........

cheers
Ramanjaneyulu Vuta.

Give me feedback.